JP-2000-323613-A (which corresponds to U.S. Pat. No. 6,418,615) proposes a multilayer circuit board for a semiconductor device shown in FIG. 13. The multilayer circuit board 100 for a semiconductor device shown in FIG. 13 includes a multilayer circuit board body 105 having conductor wiring lines 102 stacked with intervening insulating layers 104 made of a resin such as polyimide or polyphenylene ether. One side of the multilayer circuit board body 105 is a side for mounting a semiconductor element thereon, on which side pads 120a for connecting to a semiconductor element, to which the electrode terminals 108 of a semiconductor element 106 to be mounted is to be connected, are formed, and the other side of the multilayer circuit board body 105 is a side for fixing external connecting terminals thereon, on which side pads 124 for external connecting terminals, on each of which a solder ball 122, as an external connecting terminal, is to be fixed, are formed. The semiconductor element-mounting side and the external connecting terminal-fixing side of the multilayer circuit board body 105 are covered with a solder resist 126, except for the semiconductor element-connecting pads 120a and the pads 124 for external connecting terminals.
In such a multilayer circuit board body 105, the conductor wiring lines 102 and/or the pads (the pads 120 for connecting layers of wiring lines to each other, the pads 124 for external connecting terminals, or the semiconductor element-connecting pads 120a) are electrically connected to each other through vias 128 penetrating the insulating layers 104. The via 128 is formed in an aperture 130 which is opened at the side of an insulating layer 104 facing the external connecting terminal-fixing side, and has a bottom defined by the face of the conductor wiring line 102 or pad 120, 120a formed at the side of the insulating layer 104 facing the semiconductor element-mounting side. In addition, a frame 117 having a given strength can be joined to the periphery of the multilayer circuit board body 105, so as to improve handleability, such as ease of carriage, of the multilayer circuit board 100 for a semiconductor device.
The multilayer circuit board 100 for a semiconductor device as shown in FIG. 13 can be produced by alternately forming the conductor wiring line layer and the insulating layer from the layer for mounting a semiconductor element having a face for mounting the semiconductor element in the direction of the layer for fixing external connecting terminals having a face for fixing the external connecting terminals, as described below by making reference to FIGS. 14 to 16.
First, a seed layer 142 is formed on a side of a copper sheet 140, as a metal sheet (FIG. 14A). As shown in FIG. 15, which is an enlarged view of the portion of the circle designated by A in FIG. 14A, the seed layer 142 is made of a chromium (Cr) layer 141a in direct contact with one face of the copper sheet 140, and a copper (Cu) layer 141b formed on the chromium layer 141a. 
A photoresisit pattern (not shown) is formed on the seed layer 142 formed on the one face of the copper sheet 140, portions of the seed layer 142 at which semiconductor element-connecting pads 120a are to be formed are exposed, and semiconductor element-connecting pads 120a made of copper, to which the electrode terminals 108 of a semiconductor element 106 (FIG. 13) are subsequently connected, are then formed by electroplating using the seed layer 142, particularly the copper layer 141b, as a power supply layer (FIG. 14B).
A polyimide resin, which is a thermosetting resin, is applied by printing or the like so as to cover the semiconductor element-connecting pads 120a thus formed, and is cured to form an insulating layer 104 (FIG. 14C). Subsequently, openings 130 are formed in the insulating layer 104 by a beam of laser light, such as light of a YAG laser or a carbon dioxide laser (FIG. 14D).
A seed layer 142′ made of a chromium layer and a copper layer is formed on the entire surface of the insulating layer 104 (FIG. 14E), including the faces of the inside walls of the openings 130 formed. Next, members representing vias 128 and conductor wiring lines 102 (FIG. 13) are formed using a resist pattern (not shown) formed on the seed layer 142′ as a mask and by electroplating using the seed layer 142′ as a power supply layer.
As shown in FIG. 14F, vias 128 and conductor wiring lines 102 are then formed on the surface of the insulating layer 104 by removing the seed layer 142′, at the portions other than members representing vias 128 and conductor wiring lines 102, by etching.
Subsequently, by repeating the steps of FIGS. 14C to 14F, the conductor wiring line layers and the insulating layers can be alternately formed from the side of the layer for mounting a semiconductor element having a face for mounting a semiconductor element thereon in the direction of the layer for fixing external connecting terminals having a face for fixing the external connecting terminals thereon, to provide an intermediate 100a shown in FIG. 16. The resultant intermediate 100a has a multilayer circuit board body 105 having the face for mounting a semiconductor element thereon having the semiconductor element-connecting pads 120a formed, to which face the copper sheet 140 is joined through the seed layer 142, and has, at the opposed side, pads 124 formed for external connecting terminals. The copper sheet 140 fills the role of a reinforcing sheet for the intermediate 100a, and can facilitate handling, such as carriage, of the intermediate 100a. 
To finally obtain the multilayer circuit board 100 for a semiconductor device shown in FIG. 13, it is necessary to remove the copper sheet 140 from the intermediate 100a by etching. Due to the fact that the seed layer has, as a member, the chromium layer 141a which is not etched by an etchant for the copper sheet 140, the progress of etching can be blocked during the etching of the copper sheet 140 when the etching reaches the chromium layer 141a of the seed layer 142, and the etching of the copper sheet 140 will be finished when the whole surface of the chromium layer 141a of the seed layer 142 is exposed. Subsequently, by removing the chromium layer 141a and the copper layer 141b by etching, the surfaces of the semiconductor element-connecting pads 120a can be exposed, to thereby provide the multilayer circuit board 100 for a semiconductor device shown in FIG. 13.
According to the method for producing a multilayer circuit board for a semiconductor device described making reference to FIGS. 14 to 16, a multilayer circuit board for a semiconductor device can be obtained, the multilayer circuit board has a face for mounting a semiconductor element thereon which is as flat as possible and has a thickness which is as small as possible. However, it has been found that the intermediate 110a shown in FIG. 16 can be warped due to a difference between the coefficients of thermal expansion of the copper sheet 140 and the insulating layers 104 of a resin, or the like. Subjecting a warped intermediate 110a to subsequent processing is not permitted in view of obtaining a highly reliable semiconductor device.
On the other hand, using a copper sheet 140 having a large thickness to prevent a warp takes a very long time to process in the step of removing substantially the entire copper sheet 140 by etching to expose the surface of semiconductor element-connecting pads 120a of the multilayer circuit board body 105, and cannot be industrially employed.
A warp during a production process can be prevented by forming insulating layers needed for a multilayer circuit board to be produced on one side of a copper sheet and forming the same number of insulating layers, as dummy layers, on the other side, to form the same number of insulating layers on both sides of the copper sheet. However, the insulating layers formed on the other side of the copper sheet are dummy layers between which conductor wiring lines are not formed, and are primarily not needed, make the production process complex.
Thus, an object of the invention is to provide a method for producing a multilayer circuit board for a semiconductor device, whereby a multilayer circuit board for a semiconductor device having a face for mounting a semiconductor element thereon which is as flat as possible and has a thickness which is as small as possible can be readily obtained by preventing warping during the production process thereof.